? semiconductor components industries, llc, 2011 february, 2011 ? rev. 1 1 publication order number: NCN2612/d NCN2612 6-differential channel 1:2 switch for pcie 2.0 and display port 1.1 the NCN2612 is a 6 ? channel dif ferential spdt switch designed to route pci express gen2 and/or displayport 1.1a signals. due to the ultra ? low on ? state capacitance (4.1 pf typ) and resistance (7 typ), these switches have a signal bit rate (br) of 5 gbps, ideal for high frequency data signals. this switch pinout is designed to be used in atx form factor desktop pcs and is available in a space ? saving wqfn package. the NCN2612 uses 80% less quiescent power than other comprable pcie switches. features ? v dd power supply from 3 v to 3.6 v ? low supply current 250 a typ ? 6 differential channels 2:1 mux/demux ? compatible with display port 1.1a & pcie 2.0 ? data rate: supports 5 gbps ? low ron resistance: 7 typ ? low con capacitance: 4.1 pf ? space saving small wqfn ? 56 package ? this is a pb ? free device typical applications ? notebook computers ? desktop computers ? server/storage networks device package shipping ? ordering information NCN2612mttwg wqfn56 (pb ? free) 2000 / tape & reel wqfn56 case 510ak marking diagram http://onsemi.com a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. NCN2612 awlyywwg 1
NCN2612 http://onsemi.com 2 logic control figure 1. NCN2612 block diagram in_0+ out+ sel le d0+ d0 ? d1+ d1 ? d2+ d2 ? d3+ d3 ? in_0 ? in_1+ in_1 ? in_2+ in_2 ? in_3+ in_3 ? out ? x+ x ? tx0+ tx0 ? tx1+ tx1 ? tx2+ tx3+ tx3 ? aux+ aux ? hpd1 hpd2 rx0+ rx0 ? rx1+ rx1 ? tx2 ? truth table (sel control) function sel pci_express gen2 path is active (tx, rx) l digital video port is active (dx, hpdx, aux) h truth table (latch control) le internal mux select 0 respond to changes on sel 1 latched
NCN2612 http://onsemi.com 3 1 2 3 4 5 21 48 47 46 45 44 18 19 20 31 30 29 figure 2. pinout (top view) 22 23 25 26 27 28 56 55 54 53 52 51 50 49 gnd vdd hpd2 hpd1 aux ? aux+ vdd gnd gnd vdd tx0+ tx0 ? tx1+ tx1 ? vdd gnd gnd gnd gnd gnd in_0+ in_0 ? in_1+ in_1 ? sel le tx2+ tx2 ? tx3+ tx3 ? rx1+ rx1 ? 24 6 7 8 9 10 11 12 13 14 15 16 17 43 42 41 40 39 38 36 35 34 33 32 vdd in_2+ in_2 ? in_3+ in_3 ? gnd out+ out ? x+ x ? gnd vdd d0+ d0 ? d1+ d1 ? d2+ d2 ? d3+ d3 ? gnd vdd rx0+ rx0 ? 37 exposed pad on underside (solder to external gnd)
NCN2612 http://onsemi.com 4 pin function and description pin name description 6, 17, 22, 27, 34,50, 55 vdd dc supply, 3.3 v 10% 1, 11, 16, 20, 21, 28, 29, 35, 48, 49, 56 gnd power ground. exposed pad ? the exposed pad on the backside of package is internally connected to gnd. externally the exposed pad should also be user ? connected to gnd. 2 in_0+ differential input from gmch pcie outputs. in_0+ makes a differential pair with in_0 ? . 3 in_0 ? differential input from gmch pcie outputs. in_0 ? makes a differential pair with in_0+. 4 in_1+ differential input from gmch pcie outputs. in_1+ makes a differential pair with in_1 ? . 5 in_1 ? differential input from gmch pcie outputs. in_1 ? makes a differential pair with in_1+. 7 in_2+ differential input from gmch pcie outputs. in_2+ makes a differential pair with in_2 ? . 8 in_2 ? differential input from gmch pcie outputs. in_2 ? makes a differential pair with in_2+. 9 in_3+ differential input from gmch pcie outputs. in_3+ makes a differential pair with in_3 ? . 10 in_3 ? differential input from gmch pcie outputs. in_3 ? makes a differential pair with in_3+. 12 out+ pass ? through output from aux+ input when sel = 1. pass ? through output from rx0+ input when sel = 0. 13 out ? pass ? through output from aux ? input when sel = 1. pass ? through output from rx0 ? input when sel = 0. 14 x+ x+ is an analog pass ? through output corresponding to rx1+. 15 x ? x ? is an analog pass ? through output corresponding to the rx1 ? input. the path from rx1 ? to x ? must be matched with the path from rx1+ to x+. x+ and x ? form a differential pair when the pass ? through mux mode is selected. 18 sel sel controls the mux through a flow ? through latch. sel = 0 for pcie mode; sel = 1 for dp mode 19 le the latch gate is controlled by le. 43, 42 d0+, d0 ? analog pass ? through output#1 corresponding to in_0+ and in_0 ? , when sel = 1. 41, 40 d1+, d1 ? analog pass ? through output#1 corresponding to in_1+ and in_1 ? , when sel = 1. 39, 38 d2+, d2 ? analog pass ? through output#1 corresponding to in_2+ and in_2 ? , when sel = 1. 37, 36 d3+, d3 ? analog pass ? through output#1 corresponding to in_3+ and in_3 ? , when sel = 1. 54, 53 tx0+, tx0 ? analog pass ? through output#2 corresponding to in_0+ and in_0 ? when sel = 0. 52, 51 tx1+, tx1 ? analog pass ? through output#2 corresponding to in_1+ and in_1 ? when sel = 0. 47, 46 tx2+, tx2 ? analog pass ? through output#2 corresponding to in_2+ and in_2 ? when sel = 0. 45, 44 tx3+, tx3 ? analog pass ? through output#2 corresponding to in_3+ and in_3 ? when sel = 0. 26 aux+ differential input from hdmi/dp connector. aux+ makes a differential pair with aux ? . aux+ is passed through to the out+ pin when sel = 1. 25 aux ? differential input from hdmi/dp connector. aux ? makes a differential pair with aux+. aux ? is passed through to the out ? pin when sel = 1. 24 hpd1 positive low frequency hpd input handshake protocol signal. 23 hpd2 negative low frequency hpd input handshake protocol signal (normally not connected). 33 rx0+ differential input from pcie connector or device. rx0+ makes a differential pair with rx0 ? . rx0+ is passed through to the out+ pin when sel = 0. 32 rx0 ? differential input from pcie connector or device. rx0 ? makes a differential pair with rx0+. rx0 ? is passed through to the out ? pin when sel = 0. 31 rx1+ differential input from pcie connector or device. rx1+ makes a differential pair with rx1 ? . rx1+ is passed through to the x+ pin when sel = 0. 30 rx1 ? differential input from pcie connector or device. rx1 ? makes a differential pair with rx1+. rx1 ? is passed through to the x ? pin on the path that matches the rx1+ to x+ pin.
NCN2612 http://onsemi.com 5 maximum ratings parameter symbol rating unit power supply voltages v dd ? 0.5 v dd 5.3 v input/output voltage range of the switch v i & v o ? 0.7 v i v dd + 0.3 v selection pin voltages v sel ? 0.5 v i v dd + 0.3 v continuous current through one switch channel i io 120 ma maximum junction temperature (note 1) t j 150 c operating ambient temperature t a ? 40 to +85 c storage temperature range t stg ? 65 to +150 c thermal resistance, junction ? to ? air (note 2) r ja 37 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded. 2. this parameter is based on eia/jedec 51 ? 7 with a 4 ? layer pcb, 80mm x 80mm, two 1oz cu material internal planes and top planes of 2oz cu material.
NCN2612 http://onsemi.com 6 electrical characteristics (v dd = +3.3v 10%, t a = ? 40 c to +85 c and t j up to 125 c, unless otherwise noted. all typical values are at v dd = +3.3 v, t a = +25 c, unless otherwise noted) symbol characteristics conditions min typ max unit power supply v dd supply voltage range 3.0 3.3 3.6 v i dd power supply current v dd = 3.6 v, v in = gnd or v dd 250 500 a data switch performance (for both pcie and display port applications, unless otherwise noted) v in data input/output voltage range ? 0.1 v dd v r on on resistance (tx, rx) v dd = 3 v, 0 v v in v dd , i in = 40 ma 7 13 r on on resistance (dx,hp- dx,aux) v dd = 3 v, 0 v v in v dd , i in = 40 ma 7.5 13 r on(flat) on resistance flatness v dd = 3 v, 0 v vin v dd , i in = 40 ma 0.1 1.24 r on on resistance matching (tx, rx) v dd = 3 v, v in = 0 v, i in = 40 ma 0.35 r on on resistance matching (dx,hpdx,aux) v dd = 3 v, v in = 0 v, i in = 40 ma 0.35 c on on capacitance f = 1 mhz, switch on, open output 4.1 pf c off off capacitance f = 1 mhz, switch off 2.6 pf i on on leakage current (in_/ x_/out_) v dd = +3.6 v, v in_ = vx_ = v out_ = 0 v, +1.2 v; v d_ or v tx_ or v hpd_ or v rx_ or v aux_ = unconnected ? 1 +1 a i off off leakage current (d_/ tx_/ hpd_ / rx_/ aux_) v dd = +3.6 v, v in_ = v x_ = v out_ = 0 v, +1.2 v; v d_ or v tx_ , v hpd_ / aux_ or v rx_ = 1.2 v, 0 v ? 1 +1 a control logic characteristics (sel and le pins) v il off voltage input 0 0.8 v v ih high voltage input 2 v dd v i in off voltage input v in = 0 v or v dd ? 1 +1 a c in high voltage input f = 1 mhz 1 pf dynamic characteristics br signal data rate r s = r l = 100 differential 5 gbps i loss differential insertion loss r s = r l = 50 , f = 2.7 ghz ? 4 db r s = r l = 50 , f = 5 ghz ? 7 r s = r l = 50 , f = 7.5 ghz ? 13 v iso differential off isolation r s = r l = 50 , f = 100 mhz ? 41 db r s = r l = 50 , f = 1.35 ghz ? 19 r s = r l = 50 , f = 3 ghz ? 16 x talk differential crosstalk r s = r l = 50 , f = 2.5 ghz ? 27 db r s = r l = 50 , f = 5 ghz ? 20 r s = r l = 50 , f = 7.5 ghz ? 10
NCN2612 http://onsemi.com 7 switching characteristics (v dd = +3.3 v, t a = 25 c, unless otherwise specified) symbol characteristics conditions min typ max unit t sk1 bit ? to ? bit skew within same differential channel r s = 50 , r l = 200 , c l = 4 pf 7 ps t sk2 channel ? to ? channel skew r s = 50 , r l = 200 , c l = 4 pf 55 ps selection pins switching characteristics (v dd = +3.3 v, t a = 25 c, unless otherwise specified) symbol characteristics conditions min typ max unit t selon sel to switch turn on time vdx_a or vdx_b = +1.0 v, r l = 50 , vhpd_ x or vaux_x = +1.0 v, r l = 50 , le = v dd , c l = 100 pf 8 20 ns t seloff sel to switch turn off time vdx_a or vdx_b = +1.0 v, r l = 50 , vhpd_ x or vaux_x = +1.0 v, r l = 50 , le = v dd , c l = 100pf 5 10 ns t set le setup time sel to le vdx_a or vdx_b = +1.0 v, r l = 50 , vhpd_ x or vaux_x = +1.0 v, r l = 50 , le = v dd , c l = 100 pf 1 ns t hold le hold time le to sel vdx_a or vdx_b = +1.0 v, r l = 50 , vhpd_ x or vaux_x = +1.0 v, r l = 50 , le = v dd , c l = 100 pf 1 ns note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
NCN2612 http://onsemi.com 8 figure 3. differential insertion loss/differential return loss out+ aux ? v in+ 0.1 f port 1 NCN2612 network analyzer 50 gnd v dd x+ in_+ 50 out ? v in ? port 2 x ? in_ ? 50 rx0+ v out+ port 3 rx1+ tx+ 50 rx0 ? v out ? port 1 rx1 ? tx ? 50 aux+ 50 hpd2 50 hpd1 50 d ? 50 d+ 50 le sel +3.3v v dd 0 v figure 4. differential off ? isolation out+ aux ? v in+ 0.1 f port 1 NCN2612 network analyzer 50 gnd v dd x+ in_+ 50 out ? v in ? port 2 x ? in_ ? 50 rx0+ v out+ port 3 rx1+ tx+ 50 rx0 ? v out ? port 1 rx1 ? tx ? 50 aux+ 50 hpd2 50 hpd1 50 d ? 50 d+ 50 le sel +3.3v v dd 0 v figure 5. differential crosstalk out+ rx0+/rx0 ? v in+ 0.1 f port 1 NCN2612 network analyzer 50 gnd v dd x+ in_+ 50 out ? v in ? port 2 x ? in_ ? 50 out+ v out+ port 3 x+ in_+ 50 out ? v out ? port 1 x ? in_ ? 50 rx1+/rx1 ? 50 tx+/tx ? 50 aux+/aux ? 50 hpd1/hpd2 50 d+/d ? 50 le sel +3.3v 0v or v dd 0 v differential insertion loss 20log v out v out v in v in differential off isolation 20log v out v out v in v in differential crosstalk 20log v out v out v in v in measurements are standardized against shorts at ic terminals. differential off ? isolation is measured between in_ and ?off? d or tx, x and ?off? hpd or rx1, out and ?off? aux or rx0 terminal on each switch under figure 3. differential on ? isolation is measured between in_ and ?on? d or tx, x and ?on? hpd or rx1, out and ?on? aux or rx0 terminal on each switch under figure 4. differential crosstalk is measured between any two pairs.
NCN2612 http://onsemi.com 9 package dimensions wqfn56 5x11, 0.5p case 510ak ? 01 issue a seating 0.15 c (a3) a a1 b 1 56 56x l 56x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.70 0.80 a1 ??? 0.05 a3 0.20 ref b 0.20 0.30 d 5.00 bsc d2 2.30 2.50 e 11.00 bsc 8.50 e2 8.30 e 0.50 bsc l 0.30 0.50 k plane soldering footprint* l1 ??? 0.15 note 4 e/2 e2 d2 note 3 detail b l1 detail a l alternate constructions l a 0.10 b c k dimensions: millimeters 5.30 8.50 2.50 0.50 0.63 0.35 56x 56x pitch 11.30 pkg outline 1 recommended a 0.10 b c 0.20 min *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCN2612/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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